The architectural state of a processing unit at any given time is represented by the values of a set of architectural registers. Each architectural register can be mapped to a physical register that stores the value for the architectural register, e.g., using a map of the relationships between architectural register numbers and physical register numbers. The value of the architectural register can be read out of the corresponding physical register or it can be modified by modifying the value in the corresponding physical register. Each instruction processed by the processing unit can therefore modify the architectural state of the machine. The architectural state of the processing unit may be checkpointed at selected times by writing identifiers of the memory locations that store data for the set of architectural registers to another memory location, such as a RAM. The checkpointed values can subsequently be written back from memory to the physical registers that correspond to the set of architectural registers, e.g., if the processing unit chose the wrong speculative path following a branch instruction and the architectural state of the processing unit needs to be rolled back to the checkpointed state. However, the amount of memory needed to checkpoint the set of architectural registers may consume a significant amount of area and/or power, depending on the number of architectural registers and the amount of information stored in each architectural register.
While the disclosed subject matter may be modified and may take alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosed subject matter to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims.